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DS31256DK
256-Channel, High-Throughput HDLC Controller Demonstration Kit
www.maxim-ic.com
GENERAL DESCRIPTION
The DS31256DK is a demonstration and evaluation kit for the DS31256 Envoy 256-channel, highthroughput HDLC controller. The DS31256DK board is a PCI-based platform that offers quick and easy evaluation of the DS31256 HDLC controller, low-cost prototyping, and rapid software development. The DS31256DK operates with a software suite that runs (R) under Microsoft Windows 95/98/NT. The PC platform must be at least a 200MHz+ Pentium II class CPU with 32MB of RAM.
Windows is a registered trademark of Microsoft Corp.
FEATURES
Headers Provide Access to Clock, Sync, and Data for 16 Physical Ports Full Source Code Windows/Windows NT GUI for Device Configuration and Evaluation Programmable PLD for Port Connectivity and Clock Generation Local Bus Header for Control and Configuration of External Devices Hardware Prototyping Area
DEMO KIT CONTENTS
CD-ROM Includes: HDLC Application Notes DS31256DK Data Sheet/Manual Installation Guide DS31256 Data Sheet Executable Evaluation Application Source Code for Driver and GUI Application
ORDERING INFORMATION
PART DS31256 DESCRIPTION Demonstration Kit
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TABLE OF CONTENTS
1. 2. 2.1 2.2 2.3 GENERAL OVERVIEW ................................................................................................................. 3 SOFTWARE ................................................................................................................................ 10 ARCHITECTURE .......................................................................................................................... 10 INTRODUCTION TO CHAT............................................................................................................. 10 CHAT GUI.................................................................................................................................. 11 Main GUI Interface--Configuration..................................................................................... 11 Show Results ..................................................................................................................... 17 Memory Viewer .................................................................................................................. 19 DMA Configuration............................................................................................................. 20 Register Access ................................................................................................................. 21
2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.4 3. 3.1
DRIVER...................................................................................................................................... 22 INSTALLATION AND GETTING STARTED................................................................................ 23 CARD INSTALLATION ................................................................................................................... 23 Windows 95 Systems ......................................................................................................... 23 Windows 98 Systems ......................................................................................................... 23 Windows NT Systems ........................................................................................................ 24
3.1.1 3.1.2 3.1.3 3.2 3.3 4.
SOFTWARE INSTALLATION........................................................................................................... 24 OPERATIONAL TEST.................................................................................................................... 24 APPENDIX A............................................................................................................................... 25
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LIST OF FIGURES
Figure 1-1. PCI Card Configuration........................................................................................................ 5 Figure 1-2. Port PLD Schematic ............................................................................................................ 6 Figure 2-1. Software Architecture ........................................................................................................ 10 Figure 2-2. Software Main GUI ............................................................................................................ 11 Figure 2-3. Show Results GUI ............................................................................................................. 17 Figure 2-4. Memory Viewer GUI .......................................................................................................... 19 Figure 2-5. DMA Configuration GUI ..................................................................................................... 20 Figure 2-6. Registers Access GUI ....................................................................................................... 21 Figure 2-7. Low-Level API Source Block Relationships ....................................................................... 22
LIST OF TABLES
Table 1-A. Header A Definition .............................................................................................................. 7 Table 1-B. Header B Definition .............................................................................................................. 8 Table 1-C. Header C Definition.............................................................................................................. 9 Table 2-A. Low-Level API Source Block Contents ............................................................................... 22
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1. GENERAL OVERVIEW
The DS31256DK is a demonstration and evaluation kit for the DS31256 Envoy 256-channel, high-throughput HDLC controller. The DS31256DK is intended to be used in a full-size PC platform, complete with PCI. The DS31256DK operates with a software suite that runs under Microsoft Windows 95/98/NT. The PC platform must be at least a 200MHz+ Pentium II class CPU with 32MB of RAM. Figure 1-1 details an outline of the PCI board for the DS31256DK. The DS31256DK was designed to be as simple as possible but offers the flexibility to be used in a number of different configurations. The DS31256DK has all the DS31256's port and local bus pins, which are easily accessible through headers on top of the card. A second DS31256DK can also be loaded into the PC in an adjacent PCI slot to add additional functions such as: Multiple T1/E1 framers T3 line interface HSSI interface V.35 interfaces
An Altera 9000 series PLD device is connected to all port pins on the DS31256. The PLD can be loaded with various configurations through a programming port (J4) that resides on the DS31256DK. This PLD generates clocks and frame syncs as well as routes data from one port to another in a daisy-chain fashion to allow testing the device under worst-case loading (Figure 1-2). Two oscillators provide the port timing. The transmit side of a port is derived from one clock and the receive side from another, so that they can be asynchronous to one another. If the PLD is not needed, it can be tri-stated to remove it (electrically) from the board. Signals can then be sent to the DS31256 by the pin headers. The board is intended to be a full-size PCI card that can only be plugged into a 5V PCI system environment. There is a 256-pin plastic BGA socket on the board for the DS31256. Only the DS31256 operates at 3.3V. Since it cannot be guaranteed that a 3.3V supply exists in a 5V PCI system environment, the DS31256DK has a linear regulator on it (U4: LT1086) to convert from 5V to 3.3V. All of the other logic, including the PLD and oscillators, operate at 5V. If 3.3V exists on the PCI bus, the linear regulator can be removed and a 0W jumper can be installed at R97 (Figure 1-1). The JTAG pins on the DS31256 are not active on the DS31256DK. Therefore, the JTCLK, JTDI, and JTMS signals are wired to 3.3V and JTRST is wired low.
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Figure 1-1. PCI Card Configuration
J3: HEADER C (60 PINS) LOCAL BUS PLUS 12 GROUNDS (SEE TABLE 1-C)
100kW PULLUPS TO 3.3V ON LINT/LCS/LRDY/LHLDA/LIM 100kW PULLDOWNS ON LMS
PROTOTYPE AREA (AN ARRAY OF VIAS ON A 100-MIL PITCH)
J2: HEADER B (72 PINS) PORTS 8 TO 15 PLUS 12 GROUNDS (SEE TABLE 1-B)
100kW PULLDOWN ON RD/RC/TC
U4: LT1086CM-3.3 5V to 3.3V Linear Reg.
R97 PCI TEST POINTS VDD 5V 3.3V
LOCAL BUS
VSS VDD VDD VDD OPEN JRST JTMS JDI JTCLK JTDO
U1: DS31256 256-PIN BGA SOCKET
PCI BUS
28 PORTS J2: HEADER A (72 PINS) PORTS 0 TO 7 PLUS 12 GROUNDS (SEE TABLE 1-A) 100kW PULLDOWN ON RD/RC/TC
SW1: 10 Position DIP Switch to Ground
100kW PULLUP TO 5V
10
U3: PORT PLD ALTERA 9000
5
J4: PLD PROGRAMMING PORT
demokit2
OSC
OSC
8-PIN CAN OSCILLATORS (SOCKETED)
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Figure 1-2. Port PLD Schematic
ALTERA PLD DS31256
High Speed Port Clock Generator Port Clock Mux
OSC1
Low Speed Port Clock Generator
Channelized Port Sync Generator
RC RS RD TC TS TD RC RS RD TC TS TD RC RS RD TC TS TD RC RS RD TC TS TD
PORT 0
High Speed Port Clock Generator
Port Clock Mux
PORT 1
OSC2
Low Speed Port Clock Generator
Channelized Port Sync Generator
PORT 2
SW[10:1]
DIP SWITCH
SW1 - SW3: Port Mode See Table Below SW4: 0: Port 0-2 = Slow Clock 1: Port 0-2 = Fast Clock SW5: 0 : Port sync enabled 1 : Port sync disabled SW6 : 0 : Fast Clock = OSC/2 1 : Fast Clock = OSC SW7: 0 : Slow Clock = OSC 1 : Slow Clock determined by SW1-3 (See Table Below) SW8, SW9 : Not used SW10: 0 : Outputs tri-stated 1 : Outputs enabled
PORT 3
RC RS RD TC TS TD RC RS RD TC TS TD
PORT 14
PORT 15
Clock/Sync Definitions
SW7 0 0 0 0 0 1 1 1 1 1 X X SW3 0 0 0 0 1 0 0 0 0 1 1 1 SW2 0 0 1 1 0 0 0 1 1 0 0 1 SW1 0 1 0 1 0 0 1 0 1 0 1 X MODE Unchannelized (sync = low) 4 T1/E1 (sync active) 2 T1/E1 (sync active) E1 (sync active) T1 (sync active) Unchannelized (sync = low) 4 T1/E1 (sync active) 2 T1/E1 (sync active) E1 (sync active) T1 (sync active) Clock off (sync = low) Clock off (sync = low) SLOW PORT CLOCK OSC OSC OSC OSC OSC 66MHz / 6 = 11MHz 66MHz / 8 = 8.25MHz 66MHz / 16 = 4.125MHz 66MHz / 32 = 2.0625MHz 66MHz / 42 = 1.572MHz Clock driven low Clock driven low
Note 1: Switch Open = Off = High (1). Note 2: Switch Closed = On = Low (0). Note 3: OSC1 and OSC2 are recommended to be the same frequency. Note 4: The frequency of OSC1 and OSC2 supplied with the DK board is 66MHz.
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Table 1-A. Header A Definition
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 RS0 RD0 RC0 GND RS1 RD1 RC1 GND RS2 RD2 RC2 GND RS3 RD3 RC3 RS4 RD4 RC4 GND RS5 RD5 RC5 GND RS6 RD6 RC6 GND RS7 RD7 RC7 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 TS0 TD0 TC0 GND TS1 TD1 TC1 GND TS2 TD2 TC2 GND TS3 TD3 TC3 TS4 TD4 TC4 GND TS5 TD5 TC5 GND TS6 TD6 TC6 GND TS7 TD7 TC7
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Table 1-B. Header B Definition
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 RS8 RD8 RC8 GND RS9 RD9 RC9 GND RS10 RD10 RC10 GND RS11 RD11 RC11 RS12 RD12 RC12 GND RS13 RD13 RC13 GND RS14 RD14 RC14 GND RS15 RD15 RC15 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 TS8 TD8 TC8 GND TS9 TD9 TC9 GND TS10 TD10 TC10 GND TS11 TD11 TC11 TS12 TD12 TC12 GND TS13 TD13 TC13 GND TS14 TD14 TC14 GND TS15 TD15 TC15
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Table 1-C. Header C Definition
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 LD0 LD2 LD4 GND LD6 LD8 LD10 GND LD12 LD14 LIM GND LHOLD LBGACK
LCS LCLK LWR LA0 GND LA2 LA4 LA6 GND LA8 LA10 LA12 GND LA14 LA16 LA18
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60
LD1 LD3 LD5 GND LD7 LD9 LD11 GND LD13 LD15 LMS GND LHLDA LINT LRDY LBHE
LRD LA1 GND LA3 LA5 LA7 GND LA9 LA11 LA13 GND LA15 LA17 LA19
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2. SOFTWARE
2.1 Architecture
The DS31256DK software consists of a high-level piece of reference software called "Chat" that sits on top of a driver. This driver itself is composed of two discrete layers. The upper layer of the driver consists of various blocks of C code that are specific to the DS31256. These blocks contain an assortment of portable functions designed to serve as a low-level API for the Envoy. At the bottom level of the driver is the commercially available WinDriver, which interfaces with the Windows operating system to the DS31256DK's PCI hardware.
Figure 2-1. Software Architecture
Target Application (Chat) 3134.c wd.c Syswd.c Hdlc.c Dma.c drv.c l1.c services.c
WinDriver
2.2
Introduction to Chat
The DS31256DK software (Chat program) runs under a PC loaded with a Windows 95/98/NT operating system using the DS31256DK PCI card. The software includes two parts--the GUI interface (Figure 2-2) and the driver code. It is developed by Visual C++ and using WinDriver to create the driver. The software provides: a simple demonstration of the DS31256 with the ability to set the device into a number of different configurations software drivers for the DS31256 the ability to explore and load new data into the Envoy registers a utility to dump the internal Envoy registers to a file and to load Envoy from a file user-configurable DMA parameters The software does not implement all the functions available in the DS31256. The user controls the software through a main GUI interface, as shown in Figure 2-2. The software implements 16 ports, coupled with 16 independent bidirectional HDLC channels. However, if a field in the main GUI is shaded gray, the function is not available. HDLC Channel Assignment Table
PORT NUMBER 0 1 : 15 HDLC CHANNEL NUMBER 1 2 : 16
When a test is run, the Envoy transmits data that is looped back to either the same port (if local loopback is used) or to an adjacent port (if the Altera PLD is used to loop the data). The software checks the receipt of packets to ensure they are received without error (i.e., the CRC is correct). For each HDLC channel that is enabled, the software also keeps track of the number of packets sent, number of packets received, number of packets received in error, and a variety of other statistics/counts. 10 of 31
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2.3
2.3.1
Chat GUI
Main GUI Interface--Configuration
Figure 2-2. Software Main GUI
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General Configuration
The 16 ports on the Envoy are handled through a set of 16 check boxes. To save space on the screen, only four ports at a time are displayed. The user can scroll through the port boxes to access all 16 ports.
The port number's box must be checked to be enabled. If this box is not checked, the software does not configure any of the RP[n]CR or TP[n]CR registers nor any of the R[n]CFG[j] and T[n]CFG[j] registers for that port.
*
If this box is checked, the software sets the LLB bit (bit 10) in the RP[n]CR register to 1, configuring the port in loopback mode. If this box is not checked, the software clears the LLB bit.
*
Select the port mode from the drop-down box (same setting of the dip switch at the demo card): T1 24 DS0 channels and 193 RC clocks between RS sync signals E1 32 DS0 channels and 256 RC clocks between RS sync signals 4.096MHz 64 DS0 channels and 512 RC clocks between RS sync signals 8.192MHz 128 DS0 channels and 1024 RC clocks between RS sync signals Unchannelized One HDLC channel and no RS sync signals, speeds up to 10Mbps Unch-HiSpeed One HDLC high-speed channel and no RS sync signals (Ports 0-2 only), speeds up to 52MHz If one of the channelized modes (T1/E1/4.096MHz/8.192MHz) is chosen, the software configures the RSS0/RSS1 (bits 6, 7) and TSS0/TSS1 (bits 6, 7) in the RP[n]CR and TP[n]CR registers, respectively. If one of the unchannelized modes (Unchannelized/Unch-HiSpeed) is selected, the software sets the RUEN bit (bit 9) and the TUEN bit (bit 9) in the RP[n]CR and TP[n]CR registers, respectively, to 1. If the Unch-HiSpd mode (Ports 0-2 only) is selected, the software sets the RP0HS/RP1HS bit (bit 8) and the TP0HS/TP1HS bit (bit 8) in the RP[n]CR and TP[n]CR registers, respectively, to 1.
* * *
*
The user can select from number 1 to 256 which HDLC channels are assigned to each port. If the user assigns the same HDLC channel to more than one port or inputs an invalid number, or the user assigns more than one HDLC channel to one port when one of the unchannelized modes (Unchannelized/Unch-HiSpeed) is selected, an error message is displayed when the Configure button is hit. If one of the channelized modes (T1/E1/4.096MHz/8.192MHz) is selected, the software uses the input from HDLC CH box to determine how to assign the time slots. The software divides the number of HDLC channels assigned into the number of time slots for the mode selected (i.e., 24 for T1, 32 for E1, 64 for 4.096MHz, and 128 for 8.192MHz) to determine how many time slots an HDLC channel occupies. It places the first HDLC channel for the port in the port's first time slot. All subsequent time slots are placed sequentially behind the previous one without a gap. If the result is a fraction, then a fraction of an HDLC channel fills the rest of the available bandwidth.
*
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DS31256 Demonstration Kit The table below shows an example of the T1 channel setting. Eight HDLC channels are assigned to port 1. Since there are 24 time slots in a T1 interface, the software divides 24 by 8 HDLC channels to get 3 time slots per HDLC channel and, therefore, it assigns 3 time slots (3 x 64kbps = 192kbps) for each HDLC channel. HDLC channel 2 is assigned to T1 time slots 0 to 2. HDLC channel 3 is assigned to T1 timeslots 3 to 5, and so on.
HDLC CHANNEL NUMBER 2 3 4 5 6 7 8 9 TIME SLOTS ASSIGNED 0 to 2 3 to 5 6 to 8 9 to 11 12 to 14 15 to 17 18 to 20 21 to 23 CHANNEL SPEED (kbps) 192 192 192 192 192 192 192 192
*
The default CRC setting is 16-Bit CRC. The software sets the RCRC0/RCRC1 (bit 2, 3) and TCRC0/TCRC1 (bit 2, 3) in the RHCD and THCD registers, respectively.
* *
DeSelect: The user can deselect the mode setting of all 16 ports at once instead of unchecking them one by one. Select All: The user can select a desired mode for all 16 ports once instead of checking it one by one. The mode list box is enabled when SelectAll is selected. The user selects the desired mode and the software configures all 16 ports with the selected mode.
* * *
Select All: All 16 ports and loopbacks are checked Clear All: All selected ports and loopbacks are unchecked ClearLBKOnly: All checked loopbacks are unchecked.
Default value of blocks within the FIFO is 4. High and low watermarks are two (50% is the recommendation). The user can input the desired number.
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*
The software checks the maximum number of blocks that can be assigned, based on the following calculation. The full size of the FIFO is 1024 (minimum size is 4) blocks divided by the total number of HDLC channels being used. Blocks Assigned = 1024 / number of channels An error message displays if the user inputs the invalid number.
*
Transmit high watermark can be set to a value of 1 to N - 2. Receive low watermark can be set to a value of 1 to N - 1. N is the number of blocks. (Refer to Section 8 in the DS31256 data sheet for details.)
*
The user can input the desired packet size in byte and an integer packet count through the Packet Size and Packet Count edit boxes for his/her test. The Packet Size edit box defaults to 0x100 and the edit box of Packet Count defaults to 100 if the user does not input any numbers.
Control Descriptions
* Chat program sets the Envoy into a default state by issuing a software reset and then writing 0s into all indirect registers. The software also runs a register diagnostic to ensure it can correctly write and read all Envoy registers. The address of the buffer, descriptor, and queue are displayed in the message box when the process is done. If the diagnostic fails, the software creates an error message and displays it in the message box at the bottom of the main GUI interface.
*
When this button is hit, the Chat program loads the Envoy registers with the settings in the GUI interface. "Successfully configured port #" is displayed in the message box if successful.
*
The program transmits and receives packets based on the user's selections. "Test Done" is displayed in the message box when the test is done.
*
The user can stop the test any time. "Test stopped by user" is displayed in the message box when the user hits this button.
*
This brings up a screen (Figure 2-3) with detail information of the packet results.
*
This brings the Physical Memory Viewer screen up (Figure 2-4). The software prompts the user for an address, then it dumps the next 32 dwords to the screen. The user manually cancels the screen. This button is only active when a test is not being run.
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*
This brings up the DMA Configuration screen (Figure 2-5) for the user to configure the DMA by their desired values. Otherwise, the software uses default values to configure the DMA.
*
This brings up the Envoy Registers screen (Figure 2-6) for the user to read from or write into the register by hex number.
*
The software dumps the data of transmit and receive queues into a text file when it is checked.
*
The status of the process is displayed through the message box at the bottom of the main GUI.
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File Menu Descriptions
Open Save Dump Regs Save Log Dump Queues
All fields of the general configuration in the main GUI are filled from the file (that file should be saved by the software by Save under the File menu first). Copies all the selections from main GUI into a file when Save is selected. Saves the settings of all registers into a text file. The user can dump information at any time. Saves contents of the message box (at the bottom of the main GUI) into a text file. Dumps all queue data into a text file.
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2.3.2
Show Results
Figure 2-3. Show Results GUI
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Descriptions of Driver Statistics
Rx Large Buffer Supplied Rx Large Shadow Failed Rx Large Buf Fail Allocated RLBR RLBRE Rx Small Buffer Supplied Rx Small Shadow Failed Rx Small Buf Fail Allocated RSBR RSBRE RDQW RDQWE TPQR TDQW TDQWE Number of Rx large buffers used Number of Rx large shadow creation failures Number of Rx large buffer allocation failures Read from SDMA Bit 6 Read from SDMA Bit 7 Number of Rx small buffers used Number of Rx small shadow creation failures Number of Rx small buffers allocation failures Read from SDMA Bit 8 Read from SDMA Bit 9 Read from SDMA Bit 10 Read from SDMA Bit 11 Read from SDMA Bit 13 Read from SDMA Bit 14 Read from SDMA Bit 15
Descriptions of Application Statistics
Attempted Tx Total Tx Good Rx Bad Rx Data Errors DeadBeef Errors Rx Chan Data Errors Rx Sequence Errors Number of packet transmission attempted Total number of packets transmitted Number of packets received without error/problem Number of packets with errors For program debugging For program debugging Number of packets with an incorrect channel number Number of packets with an incorrect sequence number
Descriptions of HDLC Controller Statistics
Rx Done Queue (V Bit) Rx Callback Invocations Rx Done Queue Entries Read Rx-RL Number of V set occurrences in receive done-queue descriptors For program debugging Number of done-queue entries read Status bit for receive HDLC length check (RLENC) in SDMA register
The following seven items are read from receive done-queue descriptor, dword0, bits 27-29, reported at the final status of an incoming packet: Rx FIFO Overflows Rx Checksum Error Rx Long Frame Aborts Rx HDLC Frame Aborts Rx Non-Aligned Byte Rx PCI Aborts Rx Reserved State Remainder of the packet discarded CRC checksum error Max packet length exceeded; remainder of the packet discarded HDLC frame abort sequence detected Not an integral number of bytes PCI abort or parity data error Not a normal device operation event
The following four items are read from transmit done-queue descriptor, dword0, bits 26-28, reported at the final status of an outgoing packet: Tx SW Provisioning Errors Tx PCI Errors Tx Descriptor Errors Tx FIFO Errors Channel was not enabled. PCI errors; abort Either byte count = 0 or channel code inconsistent with pending queue Underflow events
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2.3.3
Memory Viewer
Figure 2-4. Memory Viewer GUI
The physical memory viewer shows all the data within the start and end address space that is allocated by the Chat program. The user can step through memory by the address box or by using the scroll up/down buttons on the right.
Fields Descriptions
Start Address End Address Display the starting address of the DMA that the program allocated in the memory Display the ending address of the DMA that the program allocated in the memory
Control Descriptions
Engage User can look at any address within the range of Start Address and End Address through the edit box;. (Input the desired physical address) and then hit the Engage button. All data displayed starts from the input physical address.
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2.3.4
DMA Configuration
Figure 2-5. DMA Configuration GUI
The DMA configuration displays default values at first, then the user can change the desired value and hit the Master Reset. The DMA in Envoy can read from the receive free queue and transmit pending queue as well as write to the receive done queue and transmit done queue. Therefore, each access of the descriptor queues are done one at a time, and sequentially.
Descriptions of Transmit DMA
Buffer Size Free Queue Size Pending Queue Done Queue Size of the transmit buffer side; maximum value = 0x1fff Number of free queues maximum value = 0xffff Size: Size of pending queue, maximum = 0x10000; FIFO: Enable/disable FIFO (TDMAQ bit 0) Size: Size of done queue in transmit DMA, maximum value = 0x10000 FIFO: Enable/disable FIFO (TDMAQ bit 2) Flush Timer: TDQFFT, maximum value = 0xffff Select DQS: HDLC packet (transmit DMA configuration RAM dword1, bit 1)
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Descriptions of Receive DMA
Buffer Large: RLBS register; maximum value = 0x1fff Small: RSBS register; maximum value = 0x1fff Offset: Receive DMA configuration RAM, dword2, bits 3-6 Size Select: Receive DMA configuration RAM dword2, bits 1 and 2 Large: Size of free queue for large buffer Buffer in Queue: Number of buffers to put into the free queue Small: Size of free queue for large buffer Buffer in Queue: Number of buffers to put into the free queue Maximum value of the free queue = 0x10000 (large + small) FIFO: Enable/disable FIFO (RDMAQ, bit 0) Size: Size of receive done queue, maximum value = 0x10000 FIFO: Enable/disable FIFO (RDMAQ, bit 4) Flush Timer: RDQFFT, maximum value = 0xffff Threshold: Receive DMA configuration RAM, dword2, bits 7-9
Free Queue
Done Queue
Control Descriptions
OK SaveFile Default The DMA settings are updated with the value from all fields. Saves all the information from the GUI into a file. Restores all fields to Envoy default values.
2.3.5
Register Access
Figure 2-6. Registers Access GUI
Field Descriptions
Register Address Indirect Select Data Value Address of data register to read/write. If the address is the indirect select register, user needs to input the value. Display the value from the register when Read button is hit or specify the value to write into the register when Write button is hit.
Control Descriptions
Done Write Read Close the screen. Prompt the user for which register address to write and the value to be written and then it writes to the register. Prompt the user for which register address to read and then it reads the register and return the value.
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2.4
Driver
The low-level API, or driver, shown in layer 2 of Figure 2-1 may be used as a starting point in systems development to speed time to market. Low-level API source blocks are summarized in Table 2-A, and relate to one another structurally as shown in Figure 2-7. Note also in this figure a grouping of three particular source files: 3134.c, syswd.c, and wd.c. These are the files that must undergo modifications if the WinDriver package is not deployed in the target system.
Table 2-A. Low-Level API Source Block Contents
SOURCE FILE syswd.c hdlc.c l1.c drv.c services.c 3134.c wd.c CONTENT/PURPOSE Interface code to WindRiver; system and memory management functions Channel management functions Port management and BERT functions Register management functions Bit manipulation functions WinDriver-generated PCI management functions Generated WinDriver code
Section 4 (Appendix A) contains reference tables listing all of the functions in each of the above code blocks. Note that some of the data structures are elaborate, and that they are defined in the header files. Usage examples can be found in the Chat demonstration code.
Figure 2-7. Low-Level API Source Block Relationships
3134.c
wd.c
syswd.c
hdlc.c
dma.c
services.c
drv.c
l1.c
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3. INSTALLATION AND GETTING STARTED
Please contact telecom.support@dalsemi.com or call 972-371-6555 if you have any technical questions, or visit our website at www.maxim-ic.com/telecom.
3.1
3.1.1
Card Installation
Windows 95 Systems
Separate instructions for Win95, Win98, and WinNT Systems.
1) Power-down the host computer system, and open its case. Follow ESD precautions while in contact with the card, the DS31256, and system components. 2) If not already seated, install the DS31256 chip into the BGA socket on the DK's PC board. 3) Set the DIP switches on the card to configure the board and operational mode (Figure 1-2). 4) Plug the DS31256DK card into an empty PCI slot. 5) Reassemble the computer. 6) Boot the computer. 7) Insert the DS31256DK1 CD. 8) Open a DOS window to perform the following commands: - Change directory to c:\windows\system\vmm32. - Copy the file windrvr.vxd from the CD "Install\Win95" directory to c:\windows\system\vmm32. - Copy the file wdreg.exe from the CD "Install\Win95" directory to c:\windows\system\vmm32. - Run wdreg -vxd install from the DOS prompt in the current working directory. - Close the DOS shell and reboot the machine.
3.1.2
Windows 98 Systems
1) Power-down the host computer system, and open its case. Follow ESD precautions while in contact with the card, the DS31256, and system components. 2) If not already seated, install the DS31256 chip into the BGA socket on the DK's PC board. 3) Set the DIP switches on the card to configure the board and operational mode (Figure 1-2). 4) Plug the DS31256DK card into an empty PCI slot. 5) Reassemble the computer. 6) Boot the computer and do not allow the system to search for or install drivers for the new hardware. 7) Insert the DS31256DK1 CD. 8) Open a DOS window to perform the following commands.: - Change directory to c:\windows\system\vmm32. - Copy the file windrvr.sys from the CD "Install\Win98" directory to c:\windows\system32\drivers. - Copy the file wdreg.exe from the CD "Install\Win98" directory to c:\windows\system32\drivers. - Run wdreg install from the DOS prompt in the current working directory. - Close the DOS shell and reboot the machine.
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3.1.3
Windows NT Systems
1) Power-down the host computer system, and open its case. Follow ESD precautions while in contact with the card, the DS31256, and system components. 2) If not already seated, install the DS31256 chip into the BGA socket on the DK's PC board. 3) Set the DIP switches on the card to configure the board and operational mode (Figure 1-2). 4) Plug the DS31256DK card into an empty PCI slot. 5) Reassemble the computer. 6) Boot the computer. 7) Insert the DS31256DK1 CD. 8) Open a DOS window to perform the following commands: - Change directory to c:\winnt\system. - Copy the file windrvr.sys from the CD "Install\WinNT" directory to c:\winnt\system32\drivers. - Copy the file wdreg.exe from the CD "Install\WinNT" directory to c:\winnt\system32\drivers. - Run wdreg install from the DOS prompt in the current working directory. - Close the DOS shell, and reboot the machine.
3.2
Software Installation
1) Make a directory on the system. 2) Copy Chat.exe from the CD "Install\" to the target directory. 3) Create a shortcut to the program, or set up a menu entry for it. Note: The source code for Chat and the underlying drivers is in the CD "Source" directory. If desired, the source directory can also be copied off of the CD to the host.
3.3
Operational Test
After performing the card and software installations as described above, 1) Ensure that the board's DIP switches are set as follows: 1 On 2 On 3 Off 4 On 5 On 6 Off 7 Off 8 Off 9 Off 10 Off
2) Execute the Chat.exe program. 3) Click the and checkbox for Port 1. 4) Make sure the Port 1 pulldown selector is set to 5) Set the Port 1 channel range from 1 to 24 mode. .
6) Set both the Packet Size and Packet Count to 100.
7) Click the 8) Click the
button. button. This results in a message stating "Successfully configured Port 1."
button. The message "Starting test with 100 packets" appears. The message "Test Done" 9) Click the prints when complete. button. In the Application Statistics portion of the results window the following 10) Next, click the data (part of them) will appear: Atempted Tx 100 Total Tx 100 Good Tx 100 Bad Tx 0 24 of 31
DS31256 Demo Kit
4. APPENDIX A
syswd.c System Services (Generated Code; see WinDriver Developer's Guide) FUNCTION SysDevOpen SysDevClose SysIntInit SysCrash SysFail SysRxBufAlloc SysRxSmBufAlloc SysRxBufFree SysRxSmBufFree sysRxBufLastFree sysTxBufAlloc sysTxBufFree sysDevWrReg16 sysDevRdReg16 sysIntDisable sysIntEnable sysMemAlloc sysMemFree sysContAlloc sysContFree locateAndOpenBoard closeBoard sysIntHandler sysClearCrashMsg SysGetCrashMsg sysGetVmemBase sysGetPmemBase sysV2P sysP2V PURPOSE Open a particular card/device on PCI Disable interrupts, unregister a card, and close the driver Configure ISR System crash error handler System failure handler Allocate receive large buffer Allocate receive small buffer Free receive large buffer Free receive small buffer Free the buffer in final Allocate transmit buffer Free transmit buffer Writes a word to an address space on the board Reads a word f rom an address space on the board Lock out interrupt thread Enable interrupt processing Allocate virtual memory Free virtual memory Allocate continuous memory block and map to phys. mem Release a continuous memory block Locate the 3134 card on the PCI bus, open it, return handle Close the 3134 board whose handle is passed Read SDMA register; then call ISR if it is not zero Clear out the crash message buffer System receive crash message Get virtual memory base address Get physical memory base address Convert virtual address to physical address Convert physical address to virtual address RETURNS int32 int32 Nothing Nothing Nothing drvRxBuf * DrvRxBuf * Nothing Nothing Nothing drvTxBuf * Nothing Nothing int32 int32 Nothing void * Nothing void * Nothing static DS3134_HANDLE Nothing Nothing Nothing Nothing unsigned long unsigned long unsigned long unsigned long
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DS31256 Demonstration Kit
hdlc.c
HDLC Functions FUNCTION hdlcDevReset hdlcDevOff hdlcChanOpen hdlcChanClose hdlcChanGetState hdlcChanTrafficCtrl hdlcChanSetDs0Bits hdlcChanClearDs0Bits PURPOSE Reset the device and its data (not called directly) Turn the device off (not called directly) Open a channel with specified parameters Close a channel Return the status of the channel Control a channel's traffic Set bits for all Ds0 of the channel Clear bits for all Ds0 of the channel RETURNS Nothing Nothing Nothing Nothing TRUE if open, FALSE otherwise Nothing Nothing Nothing
drv.c
Driver Level Functions FUNCTION drvGetVmemBase drvGetPmemBase drvVAddr2Paddr drvPAddr2Vaddr drvWriteReg drvReadReg drvWriteIReg drvReadIReg drvDevInit drvDevOff drvWrIReg drvRdIReg drvInitIRegs drvIntCallback DrvGetIsrStats drvInitIRegs DrvGetdmaDesc DrvUpdatedmaDesc PURPOSE Get virtual memory base address (calls to syswd.c) Get physical memory base address (calls to syswd.c) Convert virtual address to physical addr (calls to syswd.c) Convert physical address to virtual addr (calls to syswd.c) Write a value into a device register Read a value from a device register Write a value into an indirect register Read a value from an indirect register Reset and initialize the device Put the device in reset Write to an indirect register Read from an indirect register Write a zero to an indirect register The interrupt callback from the ISR (only DMA int.s today) Get a pointer to the interrupt service routine stats Write a zero to all indirect registers of the device Get a pointer to the structure describing DMA configuration Get a pointer to the structure of DMA updated configuration RETURNS unsigned long unsigned long unsigned long unsigned long TRUE (success) FALSE (failure) -1 on failure or the reg value on success TRUE (success) FALSE (failure) -1 on failure or the int32 reg value on success FALSE if device does not exist Nothing Nothing int32 Register value Nothing Nothing drvIsrStats * Nothing DrvDmaDesc * DrvDmaDesc *
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DS31256 Demonstration Kit L1.c Layer 1-Related Functions FUNCTION l1DevReset l1DevOff l1PortDisable l1PortInit l1PortWriteDParam l1PortSetDParamBits l1PortClearDParamBits l1PortAllocateDs0 l1PortSetDs0Bits l1PortClearDs0Bits l1PortFreeDs0 l1PortReadStatus l1PortResetV54 l1PortUnchannelizedWorkAround l1BertWriteParam l1BertSetParamBits l1BertClearParamBits l1BertLatchCounters l1BertReadCounter l1BertSetPattern l1BertSingleErrorInsertion PURPOSE Reset the device and its data (not called directly) Turn Layer 1 port off (not called directly) Disable a port Configure a port with static parameters Configure dynamic params of a port: copy from param Configure dynamic params of a port: set params corresponding to non-zero bits in param Configure dynamic params of a port:reset params corresponding to non-zero bits in param Set status specified by param, and HDLC channel number to all DS0s specified by tsMap and associate these ds0 with the port Set status specified by nonzero bits of param to all DS0s specified by bitMap Clear status specified by nonzero bits of param to all DS0s specified by bitMap Disconnect the DS0 specified by bitMap from being associated with a port Read port status and present it as a bitmap Reset V.54 Fix needed when emulating unchannelized, low speed using 8M mode Set miscellaneous BERT parameters Set miscellaneous BERT parameters defined by nonzero bits of param Set miscellaneous BERT parameters defined by nonzero bits of param Get value of coutners into local storage and start a new count Read last latched value of counter from local storage Set pattern transmission Insert single bit error Nothing Nothing Nothing Nothing Nothing Nothing Nothing Nothing Nothing Nothing Nothing Port status, int32 bitmap Nothing Nothing Nothing Nothing Nothing Nothing counter value (4 Bytes), uint32 Nothing Nothing RETURNS
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DS31256 Demonstration Kit dma.c DMA Functions FUNCTION DmaDevReset DmaDevOff DmaDevInit DmaDoRxReplenish MaDoSmRxReplenish DmaReplenishRxBuffers dmaCtrl DmaChanSend DmaRxChanCtrl DmaTxChanCtrl DmaEventRLBR DmaEventRLBRE DmaEventRSBR DmaEventRSBRE DmaEventRDQW DmaEventRDQWE DmaEventTPQR DmaEventTDQW DmaEventTDQWE dmaTxPkt DmaGetTxStats DmaGetRxStats DrvGetdmaTxDev DrvGetdmaRxDev PURPOSE Reset the device and its data (not called directly) Turn the device off Initialize the device Give the Rx DMA as many receive large buffers as it can handle (not called directly) Give the Rx DMA as many receive small buffers as it can handle (not called directly) Give the Rx DMA as many receive buffers as it can handle (not called directly) Enable or disable DMA Submit packet chain to be transmitted Set DMA RAM for the channel as appropriate Set DMA RAM for the channel as appropriate Rx large buffer read event, called by the ISR Rx large buffer read error event, called by the ISR Rx small buffer read event, called by the ISR Rx small buffer read error event, called by the ISR Rx done-queue write event, called by the ISR Rx done-queue write error event, called by the ISR Tx pending-queue read event, called by the ISR Tx done-queue write event, called by the ISR Tx done-queue write error event, called by the ISR Put a single packet into pending queue Get a pointer to the Tx DMA stats Get a pointer to the Rx DMA stats Get a pointer to the structure of DMA Tx subsystem of the device Get a pointer to the structure of DMA Rx subsystem of the device RETURNS Nothing Nothing TRUE/success, FALSE/not enough resources Nothing Nothing Nothing(calls dmaDoRxReplinish) Nothing Nothing Nothing Nothing Nothing Nothing Nothing Nothing Nothing Nothing Nothing Nothing Nothing TRUE if new pending Q element is reuqired txDmaStats * RxDmaStats * dmaTxDev * dmaRxDev *
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DS31256 Demonstration Kit
services.c General Services FUNCTION bitMapRead bitMapWrite bitMapLogicalAnd bitMapLogicalEq bitMapLogicalSubset bitMapSetBits bitMapClearBits BitMapIsEmpty BitMapSetRange BitMapClearRange Read the value of a specific bit Write the value of a specific bit Test for common set (=1) bits between two parameters Test two parameters for equivalence Test to see if parameter 2 is a subset of parameter 1 Set all bits in parameter 1 that are set in parameter 2 Clear all bits in parameter 1 that are set in parameter 2 Test to see if any bits are set in parameter 1 Set a range of bits in parameter 1 Clear a range of bits in parameter 1 PURPOSE RETURNS 0 or 1, int32 Nothing True if commonalities,else or False (int32) True if equal, else False (int32) True if subset, else False (int32) Nothing Nothing True if all bits = 0, else False (int32) Nothing Nothing
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DS31256 Demonstration Kit
ds3134.c
DS3134 Card Access Functions (Generated Code; see WinDriver Developer's Guide) FUNCTION DS3134_CountCards DS3134_Open DS3134_Close DS3134_WritePCIReg DS3134_ReadPCIReg DS3134_DetectCardElements DS3134_IsAddrSpaceActive DS3134_ReadWriteBlock DS3134_ReadByte DS3134_ReadWord DS3134_ReadDword DS3134_WriteByte DS3134_WriteWord DS3134_WriteDword DS3134_GetRegAddrs DS3134_IntIsEnabled DS3134_IntHandler DS3134_IntEnable DS3134_IntDisable PURPOSE Scan PCI and count the number of a certain type of card Open a particular card/device on PCI Disable interrupts, unregister a card, and close the driver Write to a PCI configuration register Read from a PCI configuration register Check availability of card info: interrupts, I/O, memory Check if specified address space is active Perform general block reads and writes Reads a byte from an address space on the board Reads a word from an address space on the board Reads a DWORD from an address space on the board Writes a byte to an address space on the board Writes a word to an address space on the board Writes a DWORD to an address space on the board Get register address Checks whether interrupts are enabled or not Configure interrupt event handling (indirectly called) Enable interrupt processing Disable interrupt processing RETURNS Card count, DWORD True is succesful, else False Nothing Nothing Register value, DWORD True if all are found, else False True if active, else False Nothing Byte Word DWORD Nothing Nothing Nothing Dword of 0 if found, else 1 True if enables, else False Nothing True is successfully configured, else False Nothing
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c) 2003 Maxim Integrated Products * Printed USA
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(c) 2003 Maxim Integrated Products * Printed USA
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